From bf6c7d00947ee27bfcd7ab4cde2f8ea18f231431 Mon Sep 17 00:00:00 2001
From: pml68 <contact@pml68.dev>
Date: Wed, 9 Apr 2025 22:53:40 +0200
Subject: [PATCH] fix: "`BUFFER_BINDINGS_NOT_16_BYTE_ALIGNED` not supported"
 error

---
 wgpu/src/shader/blit.wgsl | 4 ++--
 wgpu/src/triangle/msaa.rs | 4 ++++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/wgpu/src/shader/blit.wgsl b/wgpu/src/shader/blit.wgsl
index d7633808..5e600de4 100644
--- a/wgpu/src/shader/blit.wgsl
+++ b/wgpu/src/shader/blit.wgsl
@@ -8,7 +8,7 @@ var<private> uvs: array<vec2<f32>, 6> = array<vec2<f32>, 6>(
 );
 
 @group(0) @binding(0) var u_sampler: sampler;
-@group(0) @binding(1) var<uniform> u_ratio: vec2<f32>;
+@group(0) @binding(1) var<uniform> u_ratio: vec4<f32>;
 @group(1) @binding(0) var u_texture: texture_2d<f32>;
 
 struct VertexInput {
@@ -25,7 +25,7 @@ fn vs_main(input: VertexInput) -> VertexOutput {
     let uv = uvs[input.vertex_index];
 
     var out: VertexOutput;
-    out.uv = uv * u_ratio;
+    out.uv = uv * u_ratio.xy;
     out.position = vec4<f32>(uv * vec2(2.0, -2.0) + vec2(-1.0, 1.0), 0.0, 1.0);
 
     return out;
diff --git a/wgpu/src/triangle/msaa.rs b/wgpu/src/triangle/msaa.rs
index 8172575d..0bddfc09 100644
--- a/wgpu/src/triangle/msaa.rs
+++ b/wgpu/src/triangle/msaa.rs
@@ -254,6 +254,8 @@ impl Targets {
 struct Ratio {
     u: f32,
     v: f32,
+    p0: f32,
+    p1: f32,
 }
 
 pub struct State {
@@ -306,6 +308,8 @@ impl State {
         let ratio = Ratio {
             u: region_size.width as f32 / targets.size.width as f32,
             v: region_size.height as f32 / targets.size.height as f32,
+            p0: 0.0,
+            p1: 0.0,
         };
 
         if Some(ratio) != self.last_ratio {